RISC-V (pronounced “risk five”), an open-source instruction set architecture (ISA) developed at UC Berkeley and standardized in 2015, offers a free alternative to proprietary chip architectures like x86 (Intel/AMD) and ARM—enabling anyone to design, manufacture, and sell RISC-V processors without licensing fees or restrictions. By the 2020s, RISC-V gained momentum in embedded systems, IoT devices, and specialized AI chips, with China embracing it to reduce dependence on US-controlled chip technology amid geopolitical tensions. While unlikely to displace x86 or ARM in PCs and smartphones soon, RISC-V represents a shift toward open, customizable hardware ecosystems.

What RISC-V Is

An ISA defines the interface between software and hardware—the instruction set (add, subtract, load, store, etc.) that software compiles into and processors execute. x86 (Intel/AMD) and ARM dominate computing but are proprietary (requiring licenses, royalties, and restrictions). RISC-V is open: the specification is free, anyone can implement it, and there’s no licensing fees or vendor lock-in. Companies can customize and extend RISC-V for specific applications (adding AI accelerator instructions, cryptographic extensions, etc.) without permission—flexibility impossible with proprietary ISAs.

Adoption & Use Cases

Embedded systems: Western Digital, Nvidia, and others adopted RISC-V for storage controllers, GPUs’ management processors, and IoT chips—avoiding ARM licensing costs.

AI chips: Startups (SiFive, Esperanto, Tenstorrent) built RISC-V-based AI accelerators with custom machine learning instructions.

China: Alibaba’s T-Head released RISC-V server processors (2019), and Chinese companies embraced RISC-V to reduce reliance on US-controlled ARM/x86 amid trade restrictions.

Education: Universities worldwide teach RISC-V in computer architecture courses (Berkeley’s original motivation—a clean, simple ISA for teaching, unlike x86’s decades of legacy complexity).

Space: European Space Agency explored RISC-V for satellites (open design allows verification and customization for radiation tolerance).

Why It Matters

RISC-V challenges the chip industry’s proprietary model—ARM’s dominance in mobile stems from licensing control, not technical superiority. Open ISAs enable innovation without gatekeepers: startups can design custom chips without millions in licensing fees, countries can develop sovereign chip industries, and the ecosystem avoids single-vendor dependencies (if ARM’s owners restrict licenses or raise prices, alternatives exist). However, RISC-V faces a “software problem”—x86 and ARM have decades of optimized compilers, operating systems, and applications; RISC-V ecosystems are catching up but remain immature.

Geopolitical Dimension

US export controls targeting China’s chip access (blocking advanced ARM/x86 designs) accelerated RISC-V adoption as a sanction-resistant alternative. In 2023, US policymakers debated restricting American companies from contributing to RISC-V (to slow China’s progress), sparking backlash from the open-source community and highlighting tensions between open collaboration and strategic competition. RISC-V’s neutrality (governed by a Swiss foundation, RISC-V International) positions it as a global standard transcending national borders—though geopolitics may fracture that vision.

Sources: RISC-V International specifications and announcements, IEEE Spectrum RISC-V coverage, Nature Electronics open hardware analysis, SiFive/T-Head product releases